1. Field of the Invention
The present invention relates to an output circuit of a semiconductor integrated circuit and, more particularly, to an output circuit used for an insulated gate (MOS) semiconductor memory.
2. Description of the Related Art
As shown in FIG. 1, in a conventional output circuit used for a MOS memory, first and second output n-channel MOS transistors 1 and 2 are connected in series between a Vcc power source node and a Vss power source node (ground potential). The gates of the two transistors 1 and 2 receive complementary signals C and C, respectively. A series-connected point of the two transistors 1 and 2 serves as an output node.
When the signal C is set at high level "1", and the signal C is set at low level "0", the first transistor 1 is turned on and the second transistor 2 is turned off, thus setting a "1" output state. In contrast to this, when the signal C is set at low level "0", and the signal C is set at high level "1", the first transistor 1 is turned off and the second transistor 2 is turned on, thus setting a "0" output state. When both the signals C and C are set at "0" level, both the first and second MOS transistors 1 and 2 are turned off and the output node potential is set in a floating state, thus setting a high-impedance state.
As shown in FIG. 2, when the level of the signal C is rapidly changed to set the "0" output state, the second transistor 2 is rapidly turned on, and electric charges accumulated in a load capacitor connected to the output node are rapidly discharged to the Vss node. Therefore, a pulse potential at the Vss node is increased, and high-level noise is generated at the Vss node.
On the other hand, as shown in FIG. 3, in order to prevent a floating state of the output node potential when both the signals C and C are set at "0" level, external resistors R1 and R2 are often connected between the output node and the Vcc' and Vss' nodes, respectively, to set the output node at a given intermediate potential when both the signals C and C are set at "0" level.
In this output circuit, however, if the signal C rapidly goes from "1" level to "0" level to release the above-mentioned "0" output state and to set a high-impedance state while the signal C is kept at "0" level, the second transistor 2 is immediately turned off, and a current supplied from the Vcc' node to the Vss node through the resistor R1 and the second transistor 2 is rapidly cut off. In this case, voltage noise is generated at the Vss node, and a pulse potential of the Vss node is decreased. This voltage noise is defined as: EQU WV=L.(di/dt)
where L is an inductance component which is present in, e.g., a wiring layer of the Vss node, a bonding wire, or a lead frame, di is a change in current, and dt is a time change.
As described above, in the output circuit, when noise is generated to increase or decrease the pulse potential of the Vss node during "0" data output or output inversion in a "0" data output release state, other internal circuits, e.g., an input buffer IV consisting of two CMOS inverters shown in FIG. 4, formed on a single chip together with the output circuit may be erroneously operated.
In other words, assume that noise having a high-potential pulse at the Vss node is generated when an input Vin of the input buffer IV is set at, e.g., high level. A potential difference between the high-level input Vin and the Vss node is decreased, and a first inverter IV1 undesirably detects that the input Vin is set at low level. An output Vout from the first inverter IV1 is set at high level, and an output Vint from a second inverter IV2 goes to low level. As a result, an operation error of the semiconductor integrated circuit may occur.
In FIG. 1, when the level of the signal C is rapidly changed to set a "1" output state, the first transistor 1 is rapidly turned on, and a current is rapidly supplied from the Vcc node to the output node through the first transistor 1. In this case, voltage noise is generated at the Vcc node, and the potential at the Vcc node is decreased. This voltage noise is defined as: EQU WV =L.(di/dt)
where L is an inductance component which is present in, e.g., a wiring layer of the Vcc node, a bonding wire, or a lead frame, di is a change in current, and dt is a time change.
In FIG. 1, if the signal C rapidly goes from "1" level to "0" level to release the above-mentioned "1" output state and to set a high-impedance state, the first transistor 1 is immediately turned off. Also in this case, as described above, voltage noise defined as WV=L.(di/dt) is generated at the Vcc node, and the potential at the Vcc node is increased.
As described above, when noise is generated and the pulse potential of the Vcc node is decreased or increased during "1" data output or output inversion in a "1" data output release state, other internal circuits, e.g., the input buffer IV shown in FIG. 4, formed on a single chip together with the output circuit may be erroneously operated.
As multi-bit MOS memories are developed, a large number of output circuits are simultaneously operated, and a change in output current is increased. Along with this large change, noise, generated when an output from the above-mentioned output circuit is changed, is further increased. This problem is very important.